Don't have a credit card? Never mind we support BANK TRANSFER .

Log inSign up
LANGUAGE en
Menu
STOREHelp centerContactsDelivery chargesABOUT US News
SEARCH
0
Total price
0 EUR
PRICES include / exclude VAT
Homepage>IEC Standards>IEC 60191-6-20:2010 - Mechanical standardization of semiconductor devices - Part 6-20: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Measuring methods for package dimensions of small outline J-lead packages (SOJ)
download between 0-24 hoursReleased: 2010-08-30
IEC 60191-6-20:2010 - Mechanical standardization of semiconductor devices - Part 6-20: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Measuring methods for package dimensions of small outline J-lead packages (SOJ)

IEC 60191-6-20:2010

Mechanical standardization of semiconductor devices - Part 6-20: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Measuring methods for package dimensions of small outline J-lead packages (SOJ)

Normalisation mécanique des dispositifs à semiconducteurs - Partie 6-20: Règles générales pour la préparation des dessins d'encombrement des boîtiers pour dispositifs à semiconducteurs pour montage en surface - Méthodes de mesure pour les dimensions des boîtiers à sortie en J (SOJ) de faible encombrement

Format
Availability
Price and currency
English/French - Bilingual PDF
Immediate download
44.00 EUR
English/French - Bilingual Hardcopy
in stock
44.00 EUR
Standard number:IEC 60191-6-20:2010
Released:2010-08-30
Language:English/French - Bilingual
DESCRIPTION

IEC 60191-6-20:2010

IEC 60191-6-20:2010 specifies methods to measure package dimensions of small outline J-lead-packages (SOJ), package outline form E in accordance with IEC 60191-4.

Print