IEEE 1450-2023

This standard defines a test description language that: a) Facilitates the transfer of large volumes of digital test vector data from computer-aided engineering (CAE) environments to automated test equipment (ATE) environments; b) Specifies pattern, format, and timing information sufficient to define the application of digital test vectors to a device under test (DUT); c) Supports the volume of test vector data generated from structured tests such as scan/automatic test pattern generation (ATPG), integral test techniques such as built-in self test (BIST), and functional test specifications for IC designs and their assemblies, in a format optimized for application in ATE environments.

This standard addresses a need in the integrated circuit (IC) test industry to define a standard mechanism for transferring the large volumes of digital test data from the generation environment through to test. The environment today contains unique output formats of existing CAE tools, individual test environments of IC manufacturers, and proprietary IC ATE input interfaces. As each of these three arenas solves individual problems, together they have created a morass of interfaces, translators, and software environments that provide no opportunity to leverage common goals and result in much wasted efforts re-engineering solutions. As device density increases, the magnitude of test data threatens to shift the test bottleneck from the generation process to the processes necessary solely to maintain and transport this data. These two factors threaten to eliminate any productive work performed in this area unless a viable standard is defined. With a common standard for CAE and IC ATE environments, the generation, movement, and processing of this test data is greatly facilitated. This standard also allows for immediate access to test equipment supporting this standard, which benefits both ATE and IC vendors reviewing this equipment. This standard also serves as a catalyst for the development of a set of standard third party interface tools to both test and design aspects of IC device generation.

Revision Standard - Active. Standard test interface language (STIL) provides an interface between digital test generation tools and test equipment. A test description language is defined in this standard that: (a) facilitates the transfer of digital test vector data from CAE to ATE environments; (b) specifies pattern, format, and timing information sufficient to define the application of digital test vectors to a DUT; and (c) supports the volume of test vector data generated from structured tests.