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Homepage>IEEE Standards>35 INFORMATION TECHNOLOGY. OFFICE MACHINES>35.200 Interface and interconnection equipment>IEEE 1596.3-1996 - IEEE Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI)
Released: 31.07.1996

IEEE 1596.3-1996 - IEEE Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI)

IEEE Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI)

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Withdraw:10.01.2002
Standard number:IEEE 1596.3-1996
Released:31.07.1996
ISBN:978-0-7381-3136-8
Pages:34
Status:Inactive
Language:English
DESCRIPTION

IEEE 1596.3-1996

Specify a process-technology independent low voltage (less than 1V swing) to point to signal interface optimized for IEEE 1596 (SCI), using a defferential driver connected to a terminated receiver through a constant impedance transmission line.

The IEEE-1596 (SCI) standard specifies an ECL electrical interface. Although compatible with current circuit technologies, the power dissipation and cost of this interface may prevent its use on low-cost systems.

New IEEE Standard - Inactive-Withdrawn. Scalable Coherent Interface (SCI), specified in IEEE Std 1596-1992, provides computer-bus-like services but uses a collection of fast point-to-point links instead of a physical bus in order to reach far higher speeds. The base specification defines differential ECL signals, which provide a high transfer rate (16 bits are transferred every 2 ns), but are inconvenient for some applications. IEEE Std 1596.3-1996, an extension to IEEE Std 1596-1992, defines a lower-voltage differential signal (as low as 250 mV swing) that is compatible with low-voltage CMOS, BiCMOS, and GaAs circuitry. The power dissipation of the transceivers is low, since only 2.5 mA is needed to generate this differential voltage across a 100 W termination resistance. Signal encoding is defined that allows transfer of SCI packets over data paths that are 4-, 8-, 32-, 64-, and 128-bits wide. Narrow data paths (4 to 8 bits) transferring data every 2 ns can provide sufficient bandwidth for many applications while reducing the physical size and cost of the interface. The wider paths may be needed for very-high-performance systems.