IEEE C62.38-1994

The test methods described are intended to be used to discover subassembly failures that result from destructive ESD, as well as those failures that may result from modification of data stored in subassemblies [e.g., in nonvolatile memory elements such as electronically erasable programmable read-only memory (EEPROM) or battery supported random access memory (RAM)]. This guide does not specify ESD tests to characterize the withstand capability of subassemblies that are incomplete (e.g., in the process of being manufactured), nor the expected ESD immunity of externally powered and/or installed subassemblies. Also, this guide does not specify tests for completed equipment or systems, whether powered or not, nor does it specify ESD tests for individual electronic components, such as integrated circuits. Such ESD tests are covered in other standards (see IEC Pub 801-2 (1991), , , and ).

The purpose of this guide is to define test methods to evaluate the electrostatic discharge (ESD) withstand capability of finished subassemblies that have not been incorporated into the next higher-level assembly. Test methods are defined to evaluate the ability of such subassemblies to withstand ESD that occurs due to handling, shipping, and installation. These environments may not necessarily be ESD-controlled environments. Some typical electronic subassemblies are populated printed circuit boards, circuit packs, power supplies, plug-in modules, and disk drives.

New IEEE Standard - Inactive-Withdrawn. This guide establishes test methods for the evaluation of ESD withstand capability for electronic equipment subassemblies. It includes information about test conditions, test equipment, and test procedures for ESD tests of printed circuit boards and other subassemblies.