IEEE/IEC 62530-2007

This standard specifies extensions for a higher level of abstraction for modeling and verification with the Verilog® hardware description language (HDL). These additions extend Verilog into the systems space and the verification space. SystemVerilog is built on top of IEEE Std 1364™1 for the Verilog HDL. This standard includes design specification methods, embedded assertions language, testbench language including coverage and assertions application programming interface (API), and a direct programming interface (DPI). Throughout this standard, the following terms apply: — Verilog refers to IEEE Std 1364 for the Verilog HDL. — Verilog-2001 refers to IEEE Std 1364-2001 [B4]2 for the Verilog HDL. — Verilog-1995 refers to IEEE Std 1364-1995 [B3] for the Verilog HDL. — SystemVerilog refers to the extensions to the Verilog standard (IEEE Std 1364) as defined in this standard. SystemVerilog adds extended and new constructs to Verilog, including the following: — Extensions to data types for better encapsulation and compactness of code and for tighter specification — C data types: int, typedef, struct, union, enum — Other data types: bounded queues, logic (0, 1, X, Z) and bit (0, 1), tagged unions for safety — Dynamic data types: string, classes, dynamic queues, dynamic arrays, associative arrays including automatic memory management freeing users from deallocation issues — Dynamic casting and bit-stream casting — Automatic/static specification on a per-variable-instance basis — Extended operators for concise description — Wild equality and inequality — Built-in methods to extend the language — Operator overloading — Streaming operators — Set membership — Extended procedural statements — Pattern matching on selection statements for use with tagged unions — Enhanced loop statements plus the foreach statement — C-like jump statements: return, break, continue — final blocks that execute at the end of simulation (inverse of initial) — Extended event control and sequence events — Enhanced process control — Extensions to always blocks to include synthesis consistent simulation semantics — Extensions to fork…join to model pipelines and for enhanced process control — Fine-grain process control — Enhanced tasks and functions — C-like void functions — Pass by reference — Default arguments — Argument binding by name — Optional arguments — Import/export functions for DPI — Classes: object-oriented mechanism that provides abstraction, encapsulation, and safe pointer capabilities — Automated testbench support with random constraints — Interprocess communication synchronization — Semaphores — Mailboxes — Event extensions, event variables, and event sequencing — Clarification and extension of the scheduling semantics — Cycle-based functionality: clocking blocks and cycle-based attributes that help reduce development, ease maintainability, and promote reusability — Cycle-based signal drives and samples — Synchronous samples

SystemVerilog is built on top of IEEE Std 1364. SystemVerilog improves the productivity, readability, and reusability of Verilog-based code. The language enhancements in SystemVerilog provide more concise hardware descriptions, while still providing an easy route with existing tools into current hardware implementation flows. The enhancements also provide extensive support for directed and constrainedrandom testbench development, coverage-driven verification, and assertion-based verification. 1Information on references can be found in Clause 2. 2The numbers in brackets correspond to the numbers in the bibliography in Annex K. — Race-free program context — Assertion mechanism for verifying design intent and functional coverage intent — Property and sequence declarations — Assertions and coverage statements with action blocks — Extended hierarchy support — Packages for declaration encapsulation with import for controlled access — Compilation-unit scope nested modules and extern modules for separate compilation support — Extension of port declarations to support interfaces, events, and variables — $root to provide unambiguous access using hierarchical references — Interfaces to encapsulate communication and facilitate communication-oriented design — Functional coverage — DPI for clean, efficient interoperation with other languages (C provided) — Assertion API — Coverage API — Data read API — Verilog procedural interface (VPI) extensions for SystemVerilog constructs — Concurrent assertion formal semantics

New IEEE Standard - Superseded. This standard provides a set of extensions to the IEEE 1364™ Verilog® hardware description language (HDL) to aid in the creation and verification of abstract architectural level models. It also includes design specification methods, embedded assertions language, testbench language including coverage and an assertions application programming interface (API), and a direct programming interface (DPI). This standard enables a productivity boost in design and validation and covers design, simulation, validation, and formal assertion-based verification flows.